The availability of OpenCL for FPGAs along with High-Level Synthesis tools have made FPGAs an attractive platform for realizing massively parallel compute-intensive applications. FPGAs with their customizable data-path, deep pipelining abilities and enhanced power efficiency features are the most viable solutions for programming and integrating them with heterogeneous platforms. Furthermore, OpenCL for FPGAs raises many challenges which require in-depth understanding to better utilize their enormous capabilities. In this work we identify, analyze and categorize the semantic differences between the OpenCL parallelism and the execution model on FPGAs. As an end result we propose a generic taxonomy for classifying FPGA parallelism potential.
At the same time, new design challenges continue to emerge for massive thread-level parallelism on FPGAs. One major execution bottleneck is the high number of memory stalls exposed to data-path which overshadows the benefits of data-path customization. We introduce a unique approach for hiding the memory stalls on FPGAs when running massively parallel applications and present a novel LLVM-based tool for decoupling memory access from computations. To enable systematic decoupling, we use the idea of kernel parallelism and implement a new parallelism granularity that breaks down kernels to separate data-path and memory-path (memory read/write) which work concurrently to overlap the computation of current threads with the memory access of future threads (memory pre-fetching at large scale).
We next move to the Xilinx based AWS cloud platform and conduct an exhaustive study on the scalability of OpenCL coarse-grain parallelism, Compute Unit(CU) replication on cloud FPGAs. In addition we present a generic template and a front-end design exploration tool to explore and identify the optimum CU number for a given application, while hiding the programming and exploration difficulties from programmers.