Continuous scaling of complementary metal-oxide-semiconductor (CMOS) transistor technology over the past few decades following Moore’s law has led to significant enhancement in the speed and performance of computing architectures. In today’s world with high demand in data processing, the CMOS scaling is focusing more on low power, cost-effective processes, and high performance to meet the requirements of high-end computations. To meet the high computation demands, reengineered, high performance, and low power device structures were necessary, and hence field effect transistors (FET) structures have evolved from planner to multi-gate, and gate all around (GAA) structures. Also, other than the very well matured silicon electronics, advanced technologies allowing heterogeneous integration of different materials systems (e.g., Si, Ge, III–V, and II-VI groups) have been developed. Though heterogeneous integration of silicon electronics with compound semiconductors can be beneficial, such developments in hybrid integration cannot address the fundamental limitations of the pure CMOS circuits, the resistive capacitive (RC) delay associated with metallic wires, and the dielectric gate delay associated with FETs. These delays ultimately limit the data speed and energy consumption.
The shift of paradigm in computer architecture that enables significant parallelism based on a radically new communication landscape will be a remarkable breakthrough. Converging electronic and photonic integrated circuits on a single chip platform to enable functional diversification emerges as one promising approach which could be realized by taking the advantage of potential low energy and huge data capacity of optical interconnects. It has been well established that monolithic integration of electronic and photonic elements on the same chip can bring about a huge change in the process of computation though the use of photons. Due to the advanced fabrication technologies, it is now possible to integrate a large number of electronic and photonic components on a single chip to perform logic, memory, and analog functions. However, in these applications, typically the photonic components only play the roles of optical interconnect between different electronic subsystems, for instance, in a photonic dynamic random-access memory (DRAM), rather than any active roles in computation, processing, or modifying data like other analog and digital circuits.
In this research work we have explored novel applications in electronic-photonic integrated circuits of a special type of metal-semiconductor-metal (MSM) photoconductive structure known as the light effect transistor (LET) which can emulate the current voltage characteristics of a FET but with much better performances in terms of switching speed (considering carrier transit delay), energy consumption per switch and Ion/Ioff ratio, and also other optoelectronic functions like optical logic gates, optical summation, optical amplification, and optoelectronic analog operation using LETs, which cannot be done using FETs. The LET can provide extremely fast optoelectronic switching (of the order of ~ ps), and its simplistic structure does-not add unwanted parasitic and leakages which are common in all gated FETs.
To understand the superiority of LETs over FETs, particularly the potential vast performance improvement in a hybrid integrated circuit of the two types of devices, we have explored the possibilities of LETs to replace some FETs in various pure electronic circuits. Using analytical relations and simulations, we have extensively studied the effect of replacing the access FETs in a 6T SRAM (six transistor static random-access memory) structure with LETs and have made some drastic changes in the hybrid 6T FET - LET structure by replacing the whole electrical word line with an optical waveguide (OWG). We have also proposed a prototype novel hybrid 3D integration scheme for the 6T SRAM architecture where all the typical electronic and optoelectronic components (4T FET latch, access LETs, bit lines, peripherals, etc.) will be placed on a single electronic layer while photonic components (OWGs, on-chip lasers to drive the OWGs, etc.) will be placed separately on the photonic layer with regularly spaced openings that provide optical signal for switching the LETs in the electronic layer. To increase the illumination efficiency, allowing for adequate spacing, and reduce the loss due to each OWG opening, LETs from two adjacent 6T cells are grouped together and illuminated simultaneously from a single OWG opening.
The OWG structure with a large number of periodic openings for the hybrid array has been designed and simulated and optimized using the Synopsys RSoft optical design suite and the fully functional 6T hybrid SRAM bit cell with its superior performance has been designed and implemented using the mixed mode design environment of Synopsys Sentaurus TCAD.